One of the limiting factors in the continuing evolution toward smaller device semiconductor feature size and higher density has been the stringent requirements placed on photolithographic processes as line width and step heights have decreased. Various resist trimming method methods have been proposed in prior art processes to achieve more finely dimension patterns following a resist exposure and development process.
For example, several different process variables may contribute to unacceptable resist profiles. Typically a photoresist layer is applied to a semiconductor wafer surface, for example, by spin coating a resinous layer over the process surface followed by what is referred to as a ‘soft bake’ to impart structural stability to the photoresist layer. The photoresist layer is then aligned and exposed to activating light through a photomask after which the photoresist undergoes a post exposure baking (PEB) process to improve adhesion and to initiate catalyzed photoresist reactions in chemically amplified photoresists. For example, in many DUV photoresists, a photoacid generated during the exposure process is partially removed in the PEB process to remove a protecting group from the resin thereby rendering the exposed region of the photoresist soluble in a developer.
The temperature and time period of the PEB process is critical to CD control of developed resist profiles. Temperatures must typically be controlled to within about 0.1° C. to prevent CD variations due to undesirable photoresist chemical reactions.
In addition, the development process must be properly controlled to avoid additional factors adversely affecting resist profiles. For example, if the exposed resist region does not become fully soluble, resist profiles are compromised.
Various approaches have been proposed in the prior art for achieving acceptable pattern resolution in finely patterned resists, for example having a resist line width smaller than a wavelength of the exposing light source. Proposed methods have included dry etching or trimming the resist following development, a method which is increasingly limited due to difficulty in controlling the etching rate of resists to form a dimensioned pattern with the required critical dimensions.
In addition, the application of an additional overlayer of resist following development of an underlying resist has been proposed to further render soluble portions of the underlying resist to achieve a smaller underlying resist pattern. While this method has met with some success, the method requires the additional and time-consuming process steps of applying an additional layer of resist with associated baking and developing steps thereby increasing cost and reducing process wafer throughput. In addition, there is a relatively high incidence of defects due to uneven and over development.
There is therefore a need in the semiconductor device manufacturing art for improved resist patterning methods to allow smaller CD's to be achieved with reduced defects and with an improved process flow including increased process wafer throughput.
It is therefore an object of the invention to provide an improved resist patterning method to allow smaller CD's to be achieved with reduced detects and with an improved process flow including increased process wafer throughput, in addition to overcoming other shortcomings of the prior art.